1. Field
Exemplary embodiments of the present invention relate to a nonvolatile memory device and a method for fabricating the same, and more particularly, to a nonvolatile memory device including a plurality of memory cells stacked substantially perpendicularly over a substrate and a method for fabricating the same.
2. Description of the Related Art
A nonvolatile memory device maintains data stored therein even though power supply is cut off. Currently, various nonvolatile memory devices such as a NAND flash memory device and the like are widely used.
Recently, as the improvement in integration degree of a 2D nonvolatile memory device including memory cells formed as a signal layer over a silicon substrate reaches the limit, a 3D nonvolatile memory device including a plurality of memory cells stacked substantially perpendicularly from a silicon substrate has been proposed. The 3D nonvolatile memory device will be briefly described below.
A conventional 3D nonvolatile memory device includes a plurality of interlayer dielectric layers and gate electrode layers that are alternately stacked over a substrate, a plurality of pillar-shaped channels connected to the substrate through the stacked structure, and a memory layer interposed between the channel and the gate electrode layer. The memory layer may store charges while insulating the channel and the gate electrode layer. In general, the memory layer has a triple-layer structure of a tunnel insulating layer, a charge storing layer, and a charge blocking layer.
In the above-described structure, a memory layer interposed between a gate electrode layer and a channel forms a unit memory cell. Therefore, when supposing that N gate electrode layers are stacked over the substrate and M channels are arranged to pass through the N gate electrodes, M×N memory cells may be formed.
In such a structure, the channel may be formed by the following process: a hole is formed through the stacked structure through a mask and etch process and a channel layer is buried in the hole.
However, there is a limitation in reducing the width of the hole due to an exposure limit during the mask and etch process for forming the hole. Therefore, considering a limited area of the semiconductor device, the number of holes and the number of channels formed in the respective holes are inevitably limited to a predetermined number or less. When the number of channels is limited, it means that the number of memory cells to be formed is limited. Accordingly, there is a limitation in increasing the integration degree of the memory device.